Radio frequency receivers have been widely used in various electronic products such as AM and FM radios, television sets, and GPS (global positioning system) navigation devices. Typically there are multiple channels within the allocated spectrum. In order to receive the signal in a desired channel, the radio frequency input signal is usually mixed with a single-frequency signal generated by a local oscillator (LO) to translate the incoming radio frequency signal to a lower-frequency signal suitable for further processing using cost effect components and/or for superior performance. The frequency translated signal may be a baseband signal, low-IF (intermediate frequency) or IF signal. The low frequency characteristic of the frequency translated signal makes itself ideal for digital signal processing at lower clock speed to conserve power consumption. In addition, the use of digital signal processing technique provides high flexibility for processing the underlying signal. Therefore, the integrated radio receiver usually includes digital signal processing circuitry to perform the required receiving functions such as filtering, demodulation, and de-multiplexing (for FM stereo broadcast).
In order to receive a desired channel, the incoming radio frequency signal is mixed with a selected LO signal to translate the frequency of incoming radio frequency signal to a lower frequency signal. A bandpass or a low pass filter is applied to the mixed signal in order to filter out possible interfering signals. The proper mixer operation requires a desired LO signal to be generated responsive to the channel selection. The LO signal usually is generated by a clock generation circuit which typically includes a voltage controlled oscillator coupled with phase locked loop circuitry. On the other hand, the digital signal processing circuitry also requires clock signals to operate properly. The clock signals for the digital signal processing circuitry should not be change with channel selection. The frequency of clock signals for the digital signal processing (DSP) circuitry may be fixed. However, the frequency of clock signals for the digital signal processing circuitry may be changed according to different requirements such as a lower frequency to consume less power. The clock signals for the digital signal processing circuitry may be generated using a separate clock generation circuit. Nevertheless, for cost saving reason as well as space saving reason, it is preferred that the digital signal processing circuitry can share the same clock generation circuit used by the mixer to generate the LO signals.
A system and method for sharing single clock generation circuitry by the mixer and the digital signal processing circuitry is disclosed in U.S. Pat. No. 7,272,373, entitled “Ratiometric Clock Systems for Integrated Receivers and Associated Methods”. In U.S. Pat. No. 7,272,373, the clock generation circuitry generates an oscillation signal that passes through a first divider to generate mixing signals for the mixer. The oscillation signal also passes through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. In U.S. Pat. No. 7,272,373, the frequency of the digital clock signal may be changed when a channel is changed since the oscillation signal is generated according to the selected channel and the digital clock signal is divided down from the oscillation signal by an integer. It is desirable to maintain the frequency of the digital clock signal fixed regardless of the channel selection.
In light of the foregoing discussions, therefore it is desirable to provide systems for clock generation shared by the mixer and the digital signal processing circuitry. Furthermore, it is desirable to maintain the frequency of the digital clock signal fixed regardless of channel selection.